1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, a method of manufacturing a semiconductor device including a step employing a light antireflection film upon exposure.
2. Description of the Prior Art
In order to improve performance of a semiconductor integrated circuit device, a higher integration degree and a higher speed operation of a semiconductor device have been requested. Miniaturization of a MOS transistor which is as a representative semiconductor device has been requested, for instance.
In the MOS transistor, size reduction of respective constituent elements in both a width direction and a thickness direction has been advancing. There has been such tendencies that, for example, a thickness of a silicon dioxide film used as a gate insulating film is made thinner than 10 nm and depths of extension source/drain layers become less than 100 nm.
A lithography technique performs a critical role in miniaturization of the MOS transistor. In general, various patterns can be formed with the use of optical exposure technique. However, in recent, it has not been seldom that a KrF excimer laser light (248 nm) can be used to develop a miniaturized MOS transistor. It is optical reflection that becomes an issue upon utilizing such exposure technique. In patterning a light reflecting film such as metal, silicon, or the like, light reflection has been suppressed by forming a antireflection film on the light reflecting film and then coating resist thereon.
Normally there are used silicon nitride or silicon nitride oxide as material used for the antireflection film.
If such antireflection film is applied to execute patterning of a gate electrode of the MOS transistor, the antireflection film remains on the gate electrode. In many cases, the antireflection film is removed after the gate electrode has been formed.
For example, as shown in FIG. 11A, a gate insulating film 102, an impurity containing polysilicon film 103, and a antireflection film 104 are formed in sequence on a silicon substrate 101, and resist 105 is then coated on the antireflection film 104. The resist 105 is patterned via exposure and developing processes to have a planar shape of the gate electrode. Then, as shown in FIG. 11B, with the use of the patterned resist 105 as a mask, the antireflection film 104 to the gate insulating film 102 are etched. Thus, the polysilicon film 103 may serve as a date electrode 103g. In addition, impurity ions are implanted into the silicon substrate 101 for the first time with the use of The gate electrode 103g as a mask, then sidewalls are formed on both side surfaces of the gate electrode 103g, and then impurity ions are implanted into the silicon substrate 101 for the second time with the use of the gate electrode 103g and the sidewalls 106 as a mask. Shallow and low concentration impurity diffusion layers 107a, 107b are formed by the first impurity ion implantation and also deep and high concentration impurity diffusion layers are formed by the second impurity ion implantation, whereby a source layer 107s and a drain layer 107d both having an LDD structure can be constructed. Thereafter, as shown in FIG. 11C, a silicon oxide film 108 is formed by thermally oxidizing a surface of the silicon substrate 101 at about 800.degree. C. In this state, as shown in FIG. 11D, the antireflection film 104 is removed by use of a phosphoric solution.
By the way, if silicon nitride which is grown by plasma CVD is employed as material for the antireflection film 104, it is common to remove the antireflection film 104 with the use of the phosphoric solution.
However, if phosphoric acid is used to remove the antireflection film 104 made of silicon nitride, it is likely that a surface of the silicon substrate 101 is made uneven by the phosphoric acid. In addition, if the surface of the silicon substrate 101 is brought directly into contact with the phosphoric acid, such surface is susceptible to .alpha. particles due to polonium contamination to thus cause soft errors.
Therefore, as shown in FIG. 11C, commonly such a method has been employed that, prior to removal of the antireflection film 104 made of silicon nitride, a protection film (108) made of SiO.sub.2 is formed on the surface of the silicon substrate 101 by thermally oxidizing the surface of the silicon substrate 101.
In addition, since the sidewalls of the gate electrode 103g are exposed when thermal oxidation is to be carried out, insulating sidewalls 106 are formed on the sidewalls of the gate electrode 103g, as shown in FIG. 11C, in order to prevent oxidation of the sidewalls.
However, if the sidewalls 106 is made up of silicon nitride, the sidewalls 106 are made thinner and moved back simultaneously with removal of the antireflection film 104 which is also made of silicon nitride.
In the event that the sidewalls 106 are formed by such thinner layer, low concentration impurity diffusion layers 107a, 107b of the source/drain layers 107s, 107d having the LDD structure are exposed by a width X, as shown in FIG. 12. For this reason, if a silicide film 110 is formed on surfaces of the source/drain layers 107s, 107d, the silicide film 110 is superposed on the low concentration impurity diffusion layers 107a, 107b. As a result, junction breakdown is liable to cause in the low concentration impurity diffusion layers 107a, 107b.
If thermal oxidization of the surface of the silicon substrate 101 is needed, such thermal oxidization is to be performed at high temperature in the range of 700.degree. C. to 900.degree. C. As shown in FIG. 13, according to the temperature to such extent, impurity contained in the gate electrode 103g is caused to punch through the gate insulating film 102 and to diffuse into the silicon substrate 101, otherwise impurity contained in the impurity diffusion layers 107a, 107b in the silicon substrate 101 is caused to diffuse laterally. As a consequence, such a problem has been caused that a short channel effect becomes worse.